| Title | A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS |
| Authors | Lu, Fei Ma, Rui Dong, Zongyu Wang, Li Zhang, Chen Wang, Chenkun Chen, Qi Wang, X. Shawn Zhang, Feilong Li, Cheng Tang, He Cheng, Yuhua Wang, Albert |
| Affiliation | Univ Calif Riverside, Dept Elect & Comp Engn, Riverside, CA 92507 USA. Qualcomm, San Diego, CA 92121 USA. Skyworks Solut, Newbury Pk, CA 91320 USA. Fairchild Semicond, Irvine, CA 92618 USA. Univ Calif Los Angeles, Dept Elect & Engn, Los Angeles, CA 90095 USA. Univ Elect Sci & Technol China, Chengdu 610051, Peoples R China. Peking Univ, SHRIME, Shanghai 201203, Peoples R China. |
| Keywords | Behavioral modeling CMOS co-design ESD RF ICS CIRCUIT VOLTAGE |
| Issue Date | 2016 |
| Publisher | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
| Citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2016,63(10),1746-1757. |
| Abstract | This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs. |
| URI | http://hdl.handle.net/20.500.11897/458860 |
| ISSN | 1549-8328 |
| DOI | 10.1109/TCSI.2016.2581839 |
| Indexed | SCI(E) |
| Appears in Collections: | 上海微电子研究院 |
