| Title | Impacts of random telegraph noise (RTN) on the Energy-Delay tradeoffs of logic circuits |
| Authors | Zhang, Yang Jiang, Xiaobo Wang, Junyao Guo, Shaofeng Fang, Yichen Wang, Runsheng Luo, Mulong Huang, Ru |
| Affiliation | Shenzhen Graduate School, Peking University, Shenzhen, 518055, China Institute of Microelectronics, Peking University, Beijing, 100871, China Computer Science and Engineering Department, University of California, San Diego, United States |
| Issue Date | 2016 |
| Publisher | China Semiconductor Technology International Conference, CSTIC 2016 |
| Citation | China Semiconductor Technology International Conference, CSTIC 2016.Shanghai, China,2016/5/2. |
| Abstract | In this paper, the impacts of random telegraph noise (RTN) on delay and energy of digital logic circuits are studied. The conventional method of extracting logic gate delay is found inaccurate due to the bias dependency of RTN amplitude. Thus an appropriate measuring strategy is proposed, based on which the impact of single RTN on circuit delay is investigated, and non-monotonous trend against trap energy level Et is found. Furthermore, the impacts of multi RTN on Energy-Delay(ED) curves are discussed. It is found that RTN is unneglectable when performing an ED optimization. Otherwise, under-design phenomenon would occur considering delay constraint, and over-design would occur considering energy constraint. This result provide helpful guidelines for circuit design. ? 2016 IEEE. |
| URI | http://hdl.handle.net/20.500.11897/436183 |
| ISSN | 9781467388047 |
| DOI | 10.1109/CSTIC.2016.7463904 |
| Indexed | EI |
| Appears in Collections: | 深圳研究生院待认领 信息科学技术学院 |
