| Title | Impacts of Random Telegraph Noise (RTN) on Digital Circuits |
| Authors | Luo, Mulong Wang, Runsheng Guo, Shaofeng Wang, Jing Zou, Jibin Huang, Ru |
| Affiliation | Peking Univ, Inst Microelect, Beijing 100871, Peoples R China. |
| Keywords | Bit error rate (BER) dynamic variability failure probability Monte Carlo simulation oxide trap random telegraph noise (RTN) ring oscillator signal integrity SRAM |
| Issue Date | 2015 |
| Publisher | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Citation | IEEE TRANSACTIONS ON ELECTRON DEVICES.2015,62,(6),1725-1732. |
| Abstract | Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition (p(dc)), which is traditionally used for RTN characterization, ac trap occupancy probability (p(ac)), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on p(ac). The results show that degradations are highly workload dependent and that p(ac) is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design. |
| URI | http://hdl.handle.net/20.500.11897/419712 |
| ISSN | 0018-9383 |
| DOI | 10.1109/TED.2014.2368191 |
| Indexed | SCI(E) EI |
| Appears in Collections: | 信息科学技术学院 |
