| Title | Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application |
| Authors | Wang, Qida Xu, Peipei Li, Hong Liu, Fengbin Sun, Shuai Zhou, Gang Qing, Tao Zhang, Shaohua Lu, Jing |
| Affiliation | North China Univ Technol, Coll Mech & Mat Engn, Beijing 100144, Peoples R China Donghua Univ, Coll Mech Engn, Shanghai 201620, Peoples R China Beijing Inst Control Engn, Beijing Key Lab Long Life Technol Precise Rotat &, Beijing 100094, Peoples R China Peking Univ, State Key Lab Mesoscop Phys, Beijing 100871, Peoples R China Peking Univ, Dept Phys, Beijing 100871, Peoples R China Collaborat Innovat Ctr Quantum Matter, Beijing 100871, Peoples R China Peking Univ, Yangtze Delta Inst Optoelect, Nantong 226000, Peoples R China |
| Keywords | NEGATIVE CAPACITANCE MONOLAYER TRANSISTORS |
| Issue Date | Mar-2022 |
| Publisher | JOURNAL OF COMPUTATIONAL ELECTRONICS |
| Abstract | Compared with a two-dimensional (2D) homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to improve the performance of a tunnel field-effect transistor (TFET), mainly by controlling the tunneling barrier. We simulate 10-nm-L-g double-gated GeSe homojunction TFETs and van der Waals (vdW) GeSe/GeTe heterojunction TFETs based on a ballistic quasi-static ab initio quantum transport simulation. Two device configurations are considered for both the homojunction and heterojunction TFETs by placing the bilayer (BL) GeSe or vdW GeSe/GeTe heterojunction as the source or drain, while the channel and the remaining drain or source use monolayer (ML) GeSe. The on-state current (I-on) values of the optimal n-type BL GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 mu A mu m(-1), respectively, which are 50% and 64% larger thanI(on) of the ML GeSe homogeneous TFET. Notably, the device performance (I-on, intrinsic delay time tau, and power dissipation PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meets the requirements of the International Roadmap for Devices and Systems for high-performance devices for the year 2034 (2020 version). [GRAPHICS] . |
| URI | http://hdl.handle.net/20.500.11897/641652 |
| ISSN | 1569-8025 |
| DOI | 10.1007/s10825-022-01867-z |
| Indexed | SCI(E) |
| Appears in Collections: | 其他实验室 人工微结构和介观物理国家重点实验室 |
