| Title | A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance |
| Authors | Yin, Ruiyuan Li, Yue Lin, Wei Wen, Cheng P. Hao, Yilong Fu, Yunyi Wang, Maojun |
| Affiliation | Peking Univ, Inst Microelect, Beijing 100871, Peoples R China Peking Univ, Sch Phys, Beijing 100871, Peoples R China |
| Keywords | Lateral MOS devices impedance frequency dispersion border traps channel resistance |
| Issue Date | 2019 |
| Publisher | IEEE ELECTRON DEVICE LETTERS |
| Abstract | In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures. |
| URI | http://hdl.handle.net/20.500.11897/548652 |
| ISSN | 0741-3106 |
| DOI | 10.1109/LED.2019.2905857 |
| Indexed | SCI(E) EI |
| Appears in Collections: | 信息科学技术学院 物理学院 |
