| Title | Circuit-Level ESD Protection Simulation Using Behavior Models in 28nm CMOS |
| Authors | Zhang, Feilong Wang, Chenkun Lu, Fei Chen, Qi Li, Cheng Wang, Albert Li, Daguang Yu, Shaofeng Zhu, Chengyu Tang, Tianshen Cheng, Yuhua |
| Affiliation | Univ Calif Riverside, Dept Elect & Comp Engn, Riverside, CA 92521 USA. TrustChip Technol Inc, Beijing, Peoples R China. Semicond Mfg Int Corp, Shanghai, Peoples R China. Peking Univ, Shanghai Res Inst Microelect, Shanghai, Peoples R China. Peking Univ, Sch Elect Engn & Comp Sci, Beijing, Peoples R China. |
| Keywords | ESD Behavior model SPICE circuit |
| Issue Date | 2017 |
| Publisher | 2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) |
| Citation | 2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA). 2017. |
| Abstract | Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events. The new ESD circuit simulation method is validated using ICs designed and fabricated in 28nm CMOS. |
| URI | http://hdl.handle.net/20.500.11897/511901 |
| ISSN | 1946-1550 |
| Indexed | CPCI-S(ISTP) |
| Appears in Collections: | 上海微电子研究院 信息科学技术学院 |
