A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur-81.1 dBc in 0.13 mu$$ \upmu $$m CMOS technology

Abstract

This paper presents a wide-band charge-pump phase-locked loop (CPPLL) with reference spur reduction techniques. To broaden the frequency range without deteriorating phase noise, a 6-bit capacitor array-based VCO and an automatic frequency calibrator (AFC) are used. A compact loop filter technique saves the capacitor area and maintains the bandwidth. Also, a novel charge pump with dynamic current matching circuit is proposed to reduce the reference spur of the PLL. The current mismatch is less than 0.22 mu$$ \upmu $$A (0.16%) over the voltage range from 0.75 to 1.55 V. Fabricated in 0.13 mu$$ \upmu $$m CMOS technology, the proposed PLL achieves a locking range of 7.6-12.3 GHz (47.2%), with a 25 MHz frequency interval. The PLL consumes 23.3 mA from a 2.5 V supply voltage and occupies a core area of 0.92 mm x$$ \times $$ 0.72 mm. The reference spur of the proposed PLL is measured to be -81.1 dBc, and in-band phase noise reaches -110.8 dBc/Hz at 1 MHz offset frequency from the 9.5 GHz carrier frequency.