| Title | A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/ differential configurable input modes* |
| Authors | Bao, Yuanxin Ye, Le |
| Affiliation | Peking Univ, Sch Integrated Circuit, Beijing Lab Future IC Technol & Sci, Beijing, Peoples R China Peking Univ, Adv Inst Informat Technol, Hangzhou, Peoples R China |
| Keywords | DB SNDR SFDR BW |
| Issue Date | Oct-2022 |
| Publisher | MICROELECTRONICS JOURNAL |
| Abstract | This paper presents a 16-bit 300-kS/s foreground calibration successive approximation register analog-to-digital converter (SAR ADC) with single-ended/differential configurable input modes. A foreground calibration method is implemented to correct mismatch errors in a capacitive digital-to-analog converter (CDAC) and reduce the capacitor size, thereby lowering the current consumption. The total capacitor size is reduced to 10 pF from the 485.6 pF required for 16-bit matching. A self-calibrated low-offset comparator is proposed to avoid the calibration being out of range. An improved merged capacitor switching technique is proposed to realize the configuration of the single-ended/differential input modes. Compared to active single-ended-to-differential converter solutions or single-ended SAR ADCs, the proposed solution achieves a smaller chip area and better power efficiency. A prototype was fabricated in 110-nm CMOS technology. It achieves a signal-to-noise and distortion ratio of 79.8 dB and integral nonlinearity of -1.5/+1.1 LSB with no missing codes. The power consumption of the ADC from a 3-V supply is 1.07 mW. |
| URI | http://hdl.handle.net/20.500.11897/657998 |
| ISSN | 0026-2692 |
| DOI | 10.1016/j.mejo.2022.105563 |
| Indexed | EI SCI(E) |
| Appears in Collections: | 待认领 |
