| Title | A 1.2-V 2.87-mu W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC |
| Authors | Meng, Lingxin Hu, Yaopeng Zhao, Yibo Qu, Wanyuan Ye, Le Zhao, Menglian Tan, Zhichao |
| Affiliation | Zhejiang Univ, Coll Informat & Elect Engn, Hangzhou 310063, Peoples R China Zhejiang Univ, Sch Micronano Elect, Hangzhou 310063, Peoples R China Peking Univ, Adv Inst Informat Technol, Beijing 100871, Peoples R China |
| Keywords | ADAPTIVE DIGITAL CORRECTION SHAPING SAR ADC ANALOG ERRORS |
| Issue Date | Oct-2022 |
| Publisher | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Abstract | This article presents a fully dynamic 2-0 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming 2.87 mu W. It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB. |
| URI | http://hdl.handle.net/20.500.11897/655674 |
| ISSN | 0018-9200 |
| DOI | 10.1109/JSSC.2022.3208144 |
| Indexed | EI SCI(E) |
| Appears in Collections: | 待认领 |
