| Title | Design and simulation of a novel multi-floating-gate synaptic nanowire transistor for neuromorphic computing |
| Authors | Li, Xiaokang Yang, Yuancheng Chen, Gong Sun, Shuang Cai, Qifeng Dong, Xiaoqiao Xu, Xiaoyan An, Xia Li, Ming Huang, Ru |
| Affiliation | Peking Univ, Key Lab Microelect Devices & Circuits, Inst Microelect, Beijing 100871, Peoples R China. |
| Issue Date | 2018 |
| Publisher | 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) |
| Citation | 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT). 2018, 867-869. |
| Abstract | In this paper, we proposed a novel multi-floating-gate synaptic nanowire transistor which can emulate synapses behaviors such as long-term potentiation (LTP), long-term depression (LTD), integration signals from multiple pre synapses and successive synaptic weight modulation, it can also realize high density interconnection in current CMOS IC technology to build complex neural network. Meanwhile, a novel scheme was also proposed to simulate amplitude-adjustable function by properly controlling the polarity-gates. Therefore, the multiple synaptic behaviors can be realized by the proposed new device, making it a competitive candidate for neuromorphic systems. |
| URI | http://hdl.handle.net/20.500.11897/573610 |
| DOI | 10.1109/ICSICT.2018.8565016 |
| Indexed | CPCI-S(ISTP) |
| Appears in Collections: | 信息科学技术学院 |
