| Title | Impact of Gate Asymmetry on Gate-All-Around Silicon Nanovvire Transistor Parasitic Capacitance |
| Authors | Dong, Xiaoqiao Yang, Yuancheng Chen, Gong Sun, Shuang Cai, Qifeng Li, Xiaokang An, Xia Xu, Xiaoyan Zhang, Wanrong Li, Ming |
| Affiliation | Beijing Univ Technol, Fac Informat Technol, Beijing 100124, Peoples R China. Peking Univ, Inst Microelect, Key Lab Microelect Devices & Circuits, Beijing 100871, Peoples R China. Beijing Univ Technol, Fac Informat Technol, Beijing 100124, Peoples R China. Li, M (reprint author), Peking Univ, Inst Microelect, Key Lab Microelect Devices & Circuits, Beijing 100871, Peoples R China. |
| Issue Date | 2018 |
| Publisher | 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) |
| Citation | 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT). 2018, 296-298. |
| Abstract | In this paper, an analytical model is developed for parasitic gate capacitance of the gate-all-around (GAA) silicon nanowire MOSFETs (SNWT) with asymmetrical top and bottom gates. The modeling results show that the gate-to-source/drain spacer significantly impacts on the parasitic capacitance especially in the case of top-to-bottom gate misalignment. It is found that the optimized top-to-bottom gate misalignment may achieve smaller C-p/C-total so as to improve the AC performance of GAA SNWT. The developed capacitance model is more suitable for the actual process for further device design optimization. |
| URI | http://hdl.handle.net/20.500.11897/573578 |
| Indexed | CPCI-S(ISTP) |
| Appears in Collections: | 信息科学技术学院 |
