| Title | Benchmarking TFET from a circuit level perspective: Applications and guideline |
| Authors | Guo, Lingyi Ye, Le Chen, Cheng Huang, Qianqian Yang, Libo Lv, Zhu An, Xia Huang, Ru |
| Affiliation | Laboratory of Microelectronic Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing, 100871, China |
| Issue Date | 2017 |
| Publisher | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 |
| Citation | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017. 2017. |
| Abstract | Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed. ? 2017 IEEE. |
| URI | http://hdl.handle.net/20.500.11897/502293 |
| ISSN | 9781467368520 |
| DOI | 10.1109/ISCAS.2017.8051028 |
| Indexed | EI |
| Appears in Collections: | 信息科学技术学院 |
