A 6bit 4GS/s Current-steering Digital-to-Analog Converter in 40nm CMOS with Adjustable Bias and DfT Block

Abstract

In this paper, a 6-bit high-speed digital-to-analog converter (DAC) is presented. This DAC is based on a segmented architecture and has an operating speed up to 4GS/s according to the post-layout simulation results. The output waveform of this DAC is realized in a non-return-to-zero (NRZ) way. The DAC core occupies an area of 0.09mm(2) in a 40nm CMOS technology. A DfT block is introduced to relieve the speed requirement of high-speed I/O. The spurious free dynamic range (SFDR) up to 44.81dBc is achieved over Nyquist interval. The power consumption is 13mW at near Nyquist frequency.