A 6b 2b/cycle SAR ADC beyond 1GS/s with Hybrid DAC Structure and Low Kickback Noise Comparators

Abstract

In this paper, a 6b SAR ADC beyond 1GS/s with 2b/cycle conversion is implemented in a 40nm CMOS low-leakage (LL) process. Compared with conventional 2b/cycle SAR ADC, a hybrid DAC consisting of a capacitor-DAC and a resistor-DAC is adopted to increase the ratio of the speed to power consumption. Besides, a novel comparator with high speed and low kickback noise is also proposed. The comparators are organized in parallel to remove the time delay of the SA logic and the reset time of comparators. The simulation result shows the ADC achieves a SNDR of 36.36dB and 36.79dB with the power consumption of 12.5mW and 20.1mW under 1.1V supply voltage, corresponding to two operation modes of 1.35GS/s and 1.5GS/s sampling rate respectively.