| Title | Analysis and design of low power XOR-XNOR circuits |
| Authors | Lan, Jinghong Wang, Fang Ji, Lijiu Jia, Song |
| Issue Date | 2006 |
| Publisher | 开云app体育 学报 自然科学版 |
| Citation | Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Scientiarum Naturalium Universitatis Pekinensis.2006,42,(3),380-384. |
| Abstract | Two novel low power pass transistor based XOR-XNOR circuits are proposed, UPPL (Unsymmetrical Push Pull Pass Transistor Logic) and CPPL (Complementary Push Pull Pass Transistor Logic). They both input single rail signals and output dual rail signals, which can get XOR and XNOR signals simultaneously. The output signals are full swing voltage. Hspice simulation under 0.18 ??m technology 1.8 V voltage showed improvement on speed and power-delay product compared with some other circuits. Compared with the latest circuits, which was proposed by Mohamed Elgamel in 2003, the UPPL and CPPL circuits have 61.0% and 58.4% decreases on power delay product respectively without load. And with fanout three, they have 25.3% and 45.3% decreases respectively. |
| URI | http://hdl.handle.net/20.500.11897/410387 |
| ISSN | 0479-8023 |
| Indexed | EI |
| Appears in Collections: | 待认领 |
