A 6-bit 1 GS/s DAC using an area efficient switching scheme for gradient-error tolerance

Abstract

This paper presents a 6-bit current-steering DAC fabricated in 65 nm digital CMOS process. In order to compensate for the systematic errors on the current sources, a novel switching scheme is proposed which can theoretically cancel out linear and quadratic gradient errors. Its implementation only requires reasonable number of current sources without increasing in the design complexity. The measured DNL and INL are 0.012 LSB and 0.023 LSB respectively. At the sampling rate of 1 GS/s, 5.9 bit ENOB and 51.4 dB SFDR at Nyquist frequency are achieved.