Title Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors
Authors Fan, Jiewen
Li, Ming
Xu, Xiaoyan
Yang, Yuancheng
Xuan, Haoran
Huang, Ru
Affiliation Peking Univ, Inst Microelect, Key Lab Microelect Devices & Circuits, Beijing 100871, Peoples R China.
Keywords Band-to-band tunneling (BTBT)
CMOS technology
gate-induced drain leakage (GIDL)
power consumption
silicon nanowire transistors (SNWTs)
CMOS TECHNOLOGY
MOSFET
GIDL
DEVICES
DESIGN
Issue Date 2015
Publisher ieee电子器件汇刊
Citation IEEE TRANSACTIONS ON ELECTRON DEVICES.2015,62,(1),213-219.
Abstract In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter (D-nw) devices under low vertical bar V-gs vertical bar. It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices. On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high vertical bar V-gs vertical bar with relatively large D-nw. Systematic study of GIDL dependence on process parameters, including D-nw cross-sectional shape, doping, and overlap length (L-ov), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing D-nw and L-ov despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.
URI http://hdl.handle.net/20.500.11897/151941
ISSN 0018-9383
DOI 10.1109/TED.2014.2371916
Indexed SCI(E)
EI
Appears in Collections: 信息科学技术学院

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