| Issue Date | Title | Author(s) |
| 2013 | Chemical-Mechanical Polishing of Bulk Tungsten Substrate | Luo, Jin; Zhang, Yiming; Song, Lu; Chen, Shuhui; Bian, Yuan; Li, Tianyu; Hao, Yilong; Chen, Jing |
| 2013 | Development and Characterization of a Through-Multilayer TSV Integrated SRAM Module | Zhu, Yunhui; Ma, Shenglin; Sun, Xin; Fang, Runiu; Zhong, Xiao; Bian, Yuan; Chen, Meng; Chen, Jing; Miao, Min; Lu, Wengao; Jin, Yufeng |
| 2012 | Development of a Through-Stack-Via Integrated SRAM Module | Zhu, Yunhui; Sun, Xin; Ma, Shenglin; Cui, Qinghu; Zhong, Xiao; Bian, Yuan; Chen, Meng; Xiao, Yongqiang; Fang, Runiu; Liu, Zhenhua; Zhu, Zhiyuan; Gong, Xin; Chen, Jing; Miao, Min; Lu, Wengao; Jin, Yufeng |
| 2012 | Effect of Additives on Copper Electroplating Profile for TSV Filling | Zhu, Yunhui; Bian, Yuan; Sun, Xin; Ma, Shenglin; Cui, Qinghu; Zhong, Xiao; Chen, Jing; Miao, Min; Jin, Yufeng |
| 2014 | Electrical measurement and analysis of TSV/RDL for 3D integration | Sun, Xin; Fang, Runiu; Zhu, Yunhui; Zhong, Xiao; Bian, Yuan; Ma, Shenglin; Miao, Min; Chen, Jing; Wang, Yan; Jin, Yufeng |
| 2016 | Fabrication and Traceable Quality Evaluation of Fine Pitch TSV with Self-integrated Micro Heater and Thermocouple | Guan, Yong; Zeng, Qinghua; Bian, Yuan; Zhong, Xiao; Chen, Jing; Ma, Shenglin; Zhu, Yunhui; Jin, Yufeng |
| 2016 | Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration | Sun, Xin; Fang, Runiu; Zhu, Yunhui; Zhong, Xiao; Bian, Yuan; Guan, Yong; Miao, Min; Chen, Jing; Jin, Yufeng |
| 2015 | Mechanical and Electrical Reliability Assessment of Bump-less Wafer-on-Wafer Integration with One-time Bottom-up TSV Filling | Guan, Yong; Zhu, Yunhui; Zeng, Qinghua; Ma, Shenglin; Su, Fei; Bian, Yuan; Zhong, Xiao; Chen, Jing; Jin, Yufeng |
| 2012 | Parametric Study, Modeling of Etching Process and Application for Tapered Through-Silicon-Via | Ma, Shenglin; Zhong, Xiao; Bian, Yuan; Sun, Xin; Zhu, Yunhui; Chen, Jing; Miao, Min; Jin, Yufeng |
| 2012 | Process Development of a Stacked Chip Module with TSV Interconnection | Zhong, Xiao; Ma, Shenglin; Zhu, Yunhui; Bian, Yuan; Sun, Xin; Cui, Qinghu; Miao, Min; Chen, Jing; Jin, Yufeng |
| 2012 | A TSV Last Integration Approach with Wafer Level Pre-patterned Adhesive Bonding | Zhu, Yunhui; Ma, Shenglin; Sun, Xin; Cui, Qinghu; Zhong, Xiao; Bian, Yuan; Chen, Jing; Miao, Min; Jin, Yufeng |
| 2012 | Understanding Effect of Additives in Copper Electroplating Filling for Through Silicon Via | Miao, Min; Zhu, Yunhui; Bian, Yuan; Sun, Xin; Ma, Shenglin; Cui, Qinghu; Zhong, Xiao; Fang, Runiu; Chen, Jing; Jin, Yufeng |
| 2014 | A Wafer Level Through-Stack-Via Integration Process with One-time Bottom-up Copper Filling | Zhu, Yunhui; Ma, Shenglin; Sun, Xin; Fang, Runiu; Zhong, Xiao; Bian, Yuan; Guan, Yong; Chen, Jing; Miao, Min; Jin, Yufeng |
